There is continual pressure in semiconductor fabrication to reduce the area of a wafer consumed by various semiconductor devices. This is not only true for production integrated circuits (ICs), but also for test structures used to evaluate semiconductor processing and devices. Many test structures are now formed in the scribe lines used to delineate ICs from each other on a wafer. Scribe lines are the lines that are sawed to break up a wafer into the individual ICs. The less area consumed by the scribe lines means more area for active circuitry and possibly more ICs per wafer.
One typical test structure 10 is shown in FIG. 1. Test structure 10 is used to measure transistor performance. The transistor of test structure 10 consists of a polysilicon gate 12 crossing a moat region 14. Moat region 14 consists of source region 14a and drain region 14b. Probe pads 16 are placed adjacent and connect to the gate 12, source region 14a and drain region 14b. The width of the transistor is typically on the order of 10 microns and the length typically ranges from sub-0.1 .mu.m to 0.2 .mu.m. The performance of a transistor is a strong function of gate length. It is important to know the gate length of the transistor being characterized. The gate length is typically measured using top view SEM (scanning electron microscope). However, where several transistors are being characterized over several die of a wafer, SEM becomes time consuming and expensive. Therefore, electrical measurements of resistors made with the same gate material are used to measure gate length. The electrical measurements are accurate and relate well with SEM measurements. A typical test structure to measure resistance is shown in FIG. 2. The structure is essentially a four pad Kelvin structure with two pads to force the current and 2 pads to measure the voltage. Resistance, R, is then determined from the measured voltage and known current. The width of the resistor, L.sub.R, is equal to a constant*P.sub.s *W/R, where P.sub.s is the sheet resistance of the gate material. The L.sub.R and the gate length are designed to be the same.
This method, however, has inaccuracies because the two test structures (FIG. 1 and FIG. 2) are located in different parts of the die. Although LR is designed to be the same and the gate length, they end up differing by various amounts as they are located on different parts of the wafer.
Another parameter of interest in a transistor is the total lateral diffusion (TLD). FIG. 3A shows a cross-section of a typical transistor. TLD determines how fast a transistor will switch from one state to another, the device current, etc. However, it is difficult to directly measure TLD. Usually it is done by measuring the gate-to-drain capacitance, C.sub.gd and subtracting off the fringing component, C.sub.fr, which is estimated from simulation (and hence, not very accurate).
FIG. 3B shows a prior art test structure used to measure C.sub.gd and determine TLD. A series of parallel gate lines 32 cross a moat region 34. Gate lines 32 are connected to each other outside of moat region 34 and connected to a probe pad 36. Moat region 34 is also connected to a probe pad 36. Test structure 30 is typically on the order of 200.times.200 microns. To determine total capacitance, a SEM at one part, for example region 38, is measured for linewidth. That linewidth is then assumed to be uniform and used to determine the total capacitance.